This invention relates generally to integrated circuit processes and fabrication, and more particularly to a method for forming a multi-level reticle from a bi-level photoresist and for forming a phase-shifted, multi-level reticle for use in photo lithography.
The demand for progressively smaller and more powerful electronic products requires smaller geometry integrated circuits (ICs) formed on large substrates. It also creates a demand for a denser packing of circuits onto IC substrates. The requirement for smaller geometry IC circuits means that the interconnections between components and dielectric layers must be as small as possible.
Research into techniques to accomplish the forgoing has focused on various conductive and fabrication methods. Copper is a natural choice to replace aluminum, as copper has a conductivity approximately twice that of aluminum, and over three times that of tungsten. The same current may be carried through a copper line having half the cross-section of an aluminum line, and the electromigration characteristics of copper are also much superior to those of aluminum: copper is approximately ten times better than aluminum with respect to electromigration. As a result, a copper line, even one having a much smaller cross section than an aluminum line, is able to maintain electrical and mechanical integrity.
However, there are problems in the use of copper in IC processing. Copper pollutes many of the materials used in IC processes. Care must be taken to keep copper from migrating into these materials. Copper is especially prone to oxidation, especially during oxygen etch processes. Care must be take to protect copper from exposure during etching, annealing, and other high temperature processes. The oxidation products of copper are difficult to remove. Copper cannot be deposited onto substrates using the same processes as for depositing aluminum, so new deposition processes have been developed to deposit copper lines and interconnects in IC inter-level dielectrics.
Forming a copper conductor in an IC is also difficult, particularly in small geometries. It is impractical to sputter metal, either copper or aluminum, to fill small diameter vias, as both metals have poor gap filling capability. Chemical vapor deposition (CVD) has been used to deposit copper. Once deposited, however, conventional etching process methods cannot be used because the low volatility of copper etch products requires copper to be removed (vaporized) at relatively high temperatures, approximately 250xc2x0 C., which temperature will melt photoresist masks. Because of its oxidation properties, cooper cannot be removed with a plasma etch. Wet etches are isotropic, and are too imprecise for many applications. Therefore, a process to form a via using CVD without etching the copper has been developed, and is called the inlay, or damascene, process.
The damascene process for forming a via between a substrate surface and an overlying dielectric surface is described below. The underlying substrate surface is first completely covered with a dielectric, such as oxide. A reticle is a xe2x80x9chard copyxe2x80x9d of a portion of the circuit architecture formed in a thin layer of chrome on a glass or quartz substrate. The reticle may be used directly, or may be used to form a photo mask. A patterned photoresist pattern is then formed over the oxide. The photoresist pattern has an opening, or hole, in the photoresist corresponding to the area in the oxide where the via is to be formed. Other areas of the oxide to be left in place are covered with photoresist. The photoresist covered dielectric is then etched to remove oxide underlying the hole in the photoresist. The photoresist is then stripped away. CVD copper is then used to fill the via. A layer consisting of oxide with a copper via through it now overlies the substrate surface. The excess copper remaining is removed with a chemical mechanical polish (CMP) process, as is well known in the art.
Refinements in the damascene process are ongoing. One refinement is the dual damascene method. In the dual damascene method, vias, interconnects, and lines are formed in a dielectric at two different levels. In terms of the example of the damascene process in the preceding paragraph, the dual damascene process adds a second via, or interconnecting line, in the deposited oxide that extends from the new (oxide) surface to a level in the oxide between the underlying substrate surface and the new (oxide) surface. The dual damascene method is described in greater detail later herein, and in FIGS. 1 through 6.
One known method of performing the dual damascene process is through multiple photoresist mask and etch steps. A single level photoresist pattern is formed on a layer of deposited dielectric and a via pattern is formed by etching to a first inter-level in the dielectric material. At this point in the process the via is only partially etched. The photoresist is then stripped and a second, single-layer photoresist pattern is formed on the dielectric surface to form an interconnect pattern to a second inter-level in the dielectric material. Coincident with etching the interconnect, the via is etched such that interconnects in underlying substrate layers are exposed to allow electrical contact. Aligning the photoresist patterns is a problem using this method. If the two photoresist patterns are not aligned correctly, then intersecting features in the dielectric material will be misaligned. That is, a conductive line associated with the first photoresist pattern may not correctly intersect a via associated with the second photoresist pattern. Alignment errors may be corrected by making the intersecting features oversized, however, this defeats the purpose of reducing the size of connecting lines and vias. Alignment problems reduce yields, and increase the cost and the complexity of IC manufacturing processes.
Another known method of performing the dual damascene process uses photoresist patterns having multiple levels, or thicknesses, to form vias and interconnect at multiple levels in an IC dielectric. An electron beam, or laser, may be used to directly write a multi-level pattern into photoresist, but this technique is not commercially practical. So called xe2x80x9cgray-tonexe2x80x9d masks, formed from repetitive patterns of dots that appear as transparent holes on the chromium mask of the reticle, have also been used to form multi-level photoresist patterns, as described by Pierre Sixt, xe2x80x9cPhase Masks and Gray-Tone Masksxe2x80x9d, Semiconductor FabTech, 1995, page 209. Sixt also provides a general description of a process to transfer the multi-level photoresist onto a dielectric. The process relies on a one-to-one etch selectivity between the dielectric material and the photoresist material. The dielectric and the overlying photoresist pattern are then simultaneously etched, with any exposed dielectric material etched at the same rate as overlying photoresist material. Thinner layers of photoresist produce a deeper etch in the dielectric so that, after etching, the dielectric shape generally resembles the photoresist pattern overlying the dielectric at the beginning of the process.
One problem with this method is finding dielectric materials and photoresist materials that have identical etch selectivity. It is also difficult to transfer some types of features, especially small or relatively complicated features, into a dielectric using this method. Polymers and by-products of the etch process tend to collect on areas of the photoresist pattern, changing the shape and etch rates of the photoresist pattern. Further, the Sixt article states that vias made by this method have a relatively large size, approximately 25 xcexcm, due to the resolution limits imposed by the pixel size of the gray-tone mask. Vias of this size are approximately two orders of magnitude larger than vias formed through conventional methods, and are unsuited for most IC processes. A goal for VLSI structures is a via having a depth of about 1.5 xcexcm, and a width of about 0.6 xcexcm.
A multi-level photoresist pattern suitable for use in the method of the present invention is disclosed in U.S. Pat. No. 5,753,417, granted May 19, 1998, for xe2x80x9cMultiple Exposure Masking System For Forming Multi-Level Resist Profiles.xe2x80x9d A reticle for forming a multi-level photoresist pattern suitable for use with the present invention is disclosed in U.S. Pat. No. 5,936,707, granted Aug. 10, 1999, for xe2x80x9cMulti-Level Reticle System and Method for Forming Multi-level Resist Profiles.xe2x80x9d Both above mentioned patents are assigned to the same assignees as the instant application, and are incorporated herein by reference.
A method of forming a reticle includes providing a reticle blank having a quartz layer, an attenuated phase shift layer, and a metal layer; covering the reticle blank with photoresist; patterning the photoresist into multiple levels; and etching the reticle blank according to the multi-level photoresist pattern.
An object of the invention is to provide a method of forming vias and interconnects to at least two different inter-levels beneath the surface of an IC dielectric.
Another object of the invention is to perform a damascene process without concern for aligning a series of photoresist masks.
A further object of the invention is to provide a single photoresist pattern, having a plurality of levels, to reduce the number of steps and general complexity of the dual damascene method.
Another object of the invention is to provide a reticle which will phase shift light from a light source in order to achieve good contrast between exposed, partially exposed and unexposed regions for better resolution.
Yet another object of the invention is to provide an attenuated phase shift layer having a thickness which is a function of the light source wavelength for structures having a desired thickness and profile.
Another object of the invention is to provide a multi-level photoresist pattern to achieve the via widths and feature resolutions of conventional single level photoresist pattern etching processes.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.